Flash memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type.
One prior art non-volatile memory cell 10 is shown in FIG. 1. The split gate SuperFlash (SF) memory cell 10 comprises a semiconductor substrate 1 of a first conductivity type, such as P type. The substrate 1 has a surface on which there is formed a first region 2 (also known as the source line SL) of a second conductivity type, such as N type. A second region 3 (also known as the drain line) also of a second conductivity type, such as N type, is formed on the surface of the substrate 1. Between the first region 2 and the second region 3 is a channel region 4. A bit line (BL) 9 is connected to the second region 3. A word line (WL) 8 (also referred to as the select gate) is positioned above a first portion of the channel region 4 and is insulated therefrom. The word line 8 has little or no overlap with the second region 3. A floating gate (FG) 5 is over another portion of the channel region 4. The floating gate 5 is insulated therefrom, and is adjacent to the word line 8. The floating gate 5 is also adjacent to the first region 2. A coupling gate (CG) 7 (also known as control gate) is over the floating gate 5 and is insulated therefrom. An erase gate (EG) 6 is over the first region 2 and is adjacent to the floating gate 5 and the coupling gate 7 and is insulated therefrom. The erase gate 6 is also insulated from the first region 2.
One exemplary operation for erase and program of prior art non-volatile memory cell 10 is as follows. The cell 10 is erased, through a Fowler-Nordheim tunneling mechanism, by applying a high voltage on the erase gate EG 6 with other terminals equal to zero volt. Electrons tunnel from the floating gate FG 5 into the erase gate EG 6 causing the floating gate FG 5 to be positively charged, turning on the cell 10 in a read condition. The resulting cell erased state is known as ‘1’ state. Another embodiment for erase is by applying a positive voltage Vegp on the erase gate EG 6, a negative voltage Vcgn on the coupling gate CG 7, and applying a zero voltages on other terminals. The negative voltage Vcgn couples negatively the floating gate FG 5, hence less positive voltage Vcgp is required for erasing. Electrons tunnel from the floating gate FG 5 into the erase gate EG 6 causing the floating gate FG 5 to be positively charged, turning on the cell 10 in a read condition (cell state ‘1’). Alternatively, the wordline WL 8 (Vwle) and the source line SL 2 (Vsle) can be negative to further reduce the positive voltage on the erase gate FG 5 needed for erase. The magnitude of negative voltage Vwle and Vsle in this case is small enough not to forward the p/n junction.
The cell 10 is programmed, through a source side hot electron programming mechanism, by applying a high voltage on the coupling gate CG 7, a high voltage on the source line SL 2, a medium voltage on the erase gate EG 6, and a programming current on the bit line BL 9. A portion of electrons flowing across the gap between the word line WL 8 and the floating gate FG 5 acquire enough energy to inject into the floating gate FG 5 causing the floating gate FG 5 to be negatively charged, turning off the cell 10 in read condition. The resulting cell programmed state is known as ‘0’ state.
The cell 10 can be inhibited in programming (if, for instance, another cell in its row is to be programmed but cell 10 is to not be programmed) by applying an inhibit voltage on the bit line BL 9. A split gate flash memory operation and various circuitry are described in U.S. Pat. No. 7,990,773, “Sub Volt Flash Memory System,” by Hieu Van Tran, et al, and U.S. Pat. No. 8,072,815, “Array of Non-Volatile Memory Cells Including Embedded Local and Global Reference Cells and Systems,” by Hieu Van Tran, et al, which are incorporated herein by reference.
With reference to FIG. 2, a pair 20 of split gate flash memory cells is depicted. It improves layout efficiency to fabricate flash memory cells in pairs as depicted in FIG. 2. Cell 41 comprises substrate 21, bit line 23, source line 22, word line 25, control gate 27, floating gate 29, and erase gate 31. Cell 42 comprises substrate 21, bit line 24, source line 22, word line 26, control gate 28, floating gate 30, and erase gate 31. Comparing the components of FIGS. 1 and 2, in terms of function, substrate 21 operates the same as substrate 1, bit line 23 and bit line 24 operate the same as bit line 9, source line 22 operates the same as source line 2, word line 25 and word line 26 operate the same as word line 8, control gate 27 and control gate 28 operate the same as control gate 7, floating gate 29 and floating gate 30 operate the same as floating gate 5, and erase gate 31 operates the same as erase gate 6. Cell 41 and cell 42 share erase gate 31 and source line 22, and therein is the layout efficiency.
Typical operating conditions for a pair of split gate memory cells of the type shown in FIG. 2 is shown in Table 1:
TABLE 1WLBLSLCGEGSel.Unsel.Sel.Unsel.Sel.Unsel.Sel.Unsel.Sel.Unsel.Erase0 V0 V0 V0 V0 V0 V0 V0 VVee0 VReadVcc0 VVcc/20 V0 V0 VVccVcc0 V0 VProgram~1.0 V  0 V1 uAVcc~4.5 V  0 VVpp0 V4.5 V  0 V
Table 1 depicts the operating voltages required to perform the Erase, Read, and Program functions. WL refers to word line 25 or word line 26, BL refers to bit line 23 or bit line 24, SL refers to source line 22, CG refers to control gate 27 or control gate 28, and EG refers to erase gate 31. “Sel.” refers to a selected state, and “Unsel.” refers to an unselected state. Examples of values for Vcc, Vpp, and Vee are Vcc=0.8V to ˜5V, Vpp=3V to 20V, and Vee=3V to 20V.
A plurality of pairs of flash memory cells of the type shown in FIG. 2 can be arranged in two rows of cells. In FIG. 3, a first row comprises cell 101, cell 102, and cell 103. A second row comprises cell 111, cell 112, and cell 113. Cell 101 and cell 111 are pairs that follow the design of FIG. 2, and the same is true of cell 102 and cell 112, and of cell 103 and cell 113. Two rows comprising pairs of cells are referred to as a sector. In FIG. 3, sector 100 comprises cells 101, 102, 103, 111, 112, and 113. All cells in a given sector share a common source line and common erase gate. Thus, all cells in sector 100 can be erased using erase gate line 150, which is coupled to the erase gate 31 of each pair of memory cells. In FIG. 3, only six cells are shown for sector 100, but it is to be understood that a sector can include many more cells than just six.
One drawback of the prior art system is that all cells in a sector are erased at the same time. It is not possible to erase only a portion of a sector at a time. This drawback is particularly troublesome for applications such as smart cards that require a small sector size at the byte level.
What is needed is a system and method to inhibit the erasing of a portion of a sector of memory cells while allowing the remainder of the sector to be erased.